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SK Hynix HBM3 High-Performance DRAM for Data Centers, Supercomputers, and AI

2025-10-20 10:39:27 CORE View times 481

  SK Hynix's HBM3 is a high-performance DRAM designed for high-end applications such as data centers, supercomputers, and artificial intelligence.

SK Hynix's HBM3

 SK Hynix HBM3 Models:

Part No.DensityKGSD DensitySpeedPackage
H5UGJHMD83X022R16Gb192Gb5.6Gbps12Hi
H5UGJHME23X022R16Gb192Gb6.4Gbps12Hi
H5UG7HME03X020R16Gb128Gb6.0Gbps8Hi
H5UG7HMD83X020R16Gb128Gb5.6Gbps8Hi
H5UG7HME23X020R16Gb128Gb6.4Gbps8Hi

  Technical Specifications

  Capacity and Stacking: HBM3 supports up to 12-layer die stacking, representing a 1.5-fold increase in capacity compared to HBM2E. A single die can provide up to 16 GB of memory, while a single package can deliver a maximum capacity of 64 GB.

  Bandwidth: The per-die bandwidth of HBM3 can reach up to 819 GB/s. When integrated into a System-in-Package (SiP) configuration with six HBM3 dies, the aggregate bandwidth can achieve up to 4.8 TB/s, enabling robust support for large-scale parallel computing and data-intensive applications.

  Speed: HBM3 features an I/O data rate of up to 6 Gbps, which is approximately 1.8 times faster than that of HBM2E. This enhanced speed facilitates accelerated data transfer, effectively meeting the stringent requirements of high-performance computing environments.

  Power Consumption and Thermal Performance: Under identical operating voltage conditions, HBM3 operates at a lower temperature than HBM2E and exhibits superior thermal dissipation characteristics. This improved thermal efficiency allows the device to sustain higher performance levels while contributing to reduced overall system power consumption.

  Key Features

  On-Chip ECC (Error Correcting Code): HBM3 incorporates a custom-designed on-chip ECC mechanism that utilizes pre-allocated parity bits to detect and correct data errors. This function enables automatic detection and correction of single-bit errors, significantly improving data integrity and enhancing system reliability during transmission.

  Packaging Technology: HBM3 employs advanced packaging techniques involving the vertical stacking of multiple DRAM dies interconnected via Through-Silicon Via (TSV) technology. This approach not only increases chip integration density but also minimizes inter-die signal transmission delays, thereby enhancing overall system performance.

  Application Areas

  HBM3 is suitable for high-end applications that require high memory bandwidth and capacity, such as data centers, supercomputers, and artificial intelligence, significantly improving performance and efficiency in these fields.

If you need to know more about and purchase SK Hynix products, you can consult CORE customer service or fill out the RFQ.

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